The invention relates to a method according to the preamble of claim 1 for digital control of a sample clock and a system according to claim 5.
In a device performing digital signal processing, there frequently arises a need for synchronizing the computation rate with the reference clock of an external source. A good example of such a case is a data modem whose receiver is synchronized with the symbol rate of a (PAM and QAM) modulated data signal received over a transmission path. To this end, it is necessary to generate an internal clock with a controllable rate for synchronized computation. Inasmuch also the AD and DA (analog-to-digital and digital-to-analog) converters required at the respective interfaces between the analog and digital worlds are also synchronized to the same clock, the sample clocks of the converters must be designed controllable, too. In practice, sample clocks of such converters are designed to operate at a multiple of the transmission channel symbol clock rate.
A frequently used method for implementing a controllable-rate clock is to use a quartz crystal oscillator whose basic frequency can be tuned with the help of a capacitance diode incorporated in the resonant circuit of the crystal. Typically, the tuning range is in the order of a few hundred ppm (parts per million). However, a crystal oscillator has certain shortcomings. The oscillator contains a great number of components which are awkward to handle in automated production, the device occupies a large footprint on the circuit board, and it is often necessary to use several oscillators to cover desired frequencies. Furthermore, the operating frequency of crystal oscillators featuring a wide tuning range (up to a few hundred ppm) is quite limited reaching maximally to about 30 MHz.
Another generally used technique is based on the use of a digital divider of the clock frequency. Herein, a source clock operating at a high frequency is divided with the help of controllable-ratio digital divider down to the desired sample clock frequency. By adjusting the division ratio, it is possible to control the frequency and phase of the sample clock obtained by division. Such a digital division technique invariably generates jitter on the divided sample clock. Jitter impairs the accuracy of AD and DA conversions inasmuch it causes deviations in the optimal sampling timing. Frequently, the only solution to this problem is to use so high a source clock frequency that allows jitter to be reduced to an acceptable value. Nevertheless, an impossible situation arises if the maximum allowable jitter is, e.g., ±500 ps, whereby the source clock should run at about 2 GHz. Unfortunately, current ASIC technologies facilitate clocks running at 300 to 500 MHz if the ASIC itself is used for clock implementation.
In AD and DA converters based on delta-sigma modulation and switched-capacitor filters, the circuitry of the converter or filter performs sampling at a clock rate much higher than the maximum frequency of signal to be processed.